Acceleration of Design Closure and Sign-Off for 7-nm FinFET Technology

 

Check new webinar of ANSYS Software products – ANSYS Webinar.

Date – May 4, 2017, Time – 9 AM EDT / 1 PM GMT SESSION, 4 PM EDT / 8 PM GMT SESSION

Speaker –

Venue:
Online via WebEx

Contact:
webinar@ansys.com

Cost – Free

Link – Acceleration of Design Closure and Sign-Off for 7-nm FinFET Technology

Details –

Industry-leading chip designers are moving to 7nm FinFET processes to produce chips with increased functionality and performance at a comparable power envelope, while at the same time improving engineering time and reducing cost. However, attaining these benefits isn’t easy — you must also address increasingly complex design issues that affect power integrity and reliability.

About webinar –

Register now for this webinar, where our experts will demonstrate how using the right simulation tools and methodology when designing 7nm FinFET-based chips can address difficult design constraints such as shrinking margins, large design sizes and complex reliability checks.

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